1. Field of the Invention
The present invention generally relates to an electrochemical method for the identification of defects and metal contamination in silicon wafers. More specifically, the present invention relates to an electrochemical method for defect delineation in thin-film silicon-on-insulator or silicon-on-sapphire wafers. The United States Government has rights in this invention pursuant to Contract No. DE-AC04-76DP00789 between the U.S. Department of Energy and AT&T Technologies, Inc.
2. Description of Related Art
Localized clusters of defects in silicon wafers are one of the most significant limiting factors for performance and yield in integrated circuit (IC) fabrication. As a result, identification and elimination of defects are crucial for process control. Defects in silicon include point defects generated during crystal growth as well as stacking faults, dislocations and precipitates generated during processing. In addition, active IC device regions must be completely cleaned, since metal impurities such as iron, copper and nickel impair oxide integrity, reduce carrier lifetime (Hiramoto et al, Ext. Abs., 174th Electrochem. Soc. Meeting, Chicago, 1988, Abs. No. 462), and contribute to high device leakage currents (Honda et al, J. Appl. Phys., 62, 1960, (1987)). In silicon-on-insulator (SOI) fabrication, defects are generated by high fluence, high energy implantation (Separation by IMplanted OXygen-SIMOX or NItrogen-SIMNI) or by crystallization (Zone Melt Recrystallization-ZMR).
Conventional chemical defect delineation methods result in the bulk Si being etched at rates as high as 1-2 .mu.m/min, as reported in Wright Jenkins ("A new preferential etch for defects in silicon crystals," J. Electrochem. Soc.: Solid State Science and Technology, May 1977, Vol. 124, No. 5, pp. 757-762), Secco (J. Electrochem. Soc.: Solid State Science and Technology, Vol. 119, p. 948 (1972)), Sirtl et al (Z. Metallkd., Vol. 52, p. 529 (1961)), and Schimmel (J. Electrochem. Soc.: Solid State Science and Technology, Vol. 123, p. 734 (1976)). This etching rate is unacceptable for thin-film silicon-on-insulator (SOI) and silicon-on-sapphire (SOS) fabrication since the overlying Si layer may be as thin as 0.1 microns. Other conventional methods include the scanned-surface-photovoltage (SSP) technique which disadvantageously requires special instrumentation and is tedious when applied to large areas (Deines et al, "Correlation of electrolytic-etch and surface-photovoltage techniques for the detection of electrically active defects in silicon," Appl. Phys. Lett., 34(11), June 1, 1979, pp. 746-748). Accordingly, it is desirable to provide an electrochemical method for defect delineation in wafers which does not etch bulk silicon and which does not suffer from the other above-noted disadvantages.